Redundância modular dupla baseada em paridade para transmissão de dados em sistemas de processamento de bordo em Nanossatélites

Abstract

The growing demand for processing capacity in embedded systems for nanosatellites has made it common to use Commercial-Off-The-Shelf (COTS) SoCs (Systemson-Chip), which are composed of a hard-core processing unit (CPU, Central Processing Unit) and reconfigurable logic (FPGA, Field-Programmable Gate Arrays) integrated on the same chip. One point of attention in these SoCs concerns the communication interfaces between CPU and FPGA, which are implemented in the reconfigurable logic area and may suffer from errors caused by radiation in a space environment. Different types of redundancy can be employed to mitigate the effects of radiation in on-chip communication buses, highlighting information redundancy and hardware redundancy. However, despite presenting considerable correction capacity, modern information redundancy codes can present high logical complexity. Furthermore, hardware redundancy techniques such as TMR (Triple Modular Redundancy) increase the system’s area and the energy overhead. These characteristics may impact the development of nanosatellite systems, which have mass, power, weight, and cost constraints. In this context, this work presents a parity-based Dual Modular Redundancy (DMR) approach for application in COTS SoC communication interfaces, aiming at increasing data transmission reliability. To this end, it was sought to propose a solution with low logical complexity and lower area and energy consumption compared to TMR. Different versions of the technique were developed based on parity bits and DMR. For each version, mathematical expressions for the correction and error probabilities were developed, as well as the detection probability for two of the presented versions. The mathematical analysis was validated by comparisons with the results of simulations in Python scripts, considering different error rates. Furthermore, the proposed technique was compared with TMR in terms of correction probabilities. The results show that, for specific rates, the proposed approach has values close to those of TMR and that, even with the retransmission of data with possible errors, the total number of transmitted bits is lower. In order to verify the occupied area and the energy consumption, hardware implementations were performed on the Xilinx Zynq-7000 SoC. Such implementations demonstrate a lower utilization of hardware resources and energy consumption than TMR.